Windows SDCI API details for HDLC framed and transparent operation

Application Development using SDCI

SDCI is a standard interface defined by Microsoft that allows Independent Hardware Vendors to provide compatible drivers that conform to the standard Host Integration Server 2000 model. The interface provides a small set of commands to configure the link, read and write control signals, transmit and receive data, abort the transmitter or receiver etc. FarSite has enhanced the interface with a number of IOCTL's to configure and control the additional functions of the FarSync adapters including transparent continuous bitstream support.

An Application communicates with the FarSync adapter through the SDCI driver by means of Input/Output Control commands, or IOCTL's. IOCTL commands are sent from user-mode applications via the DeviceIoControl function. This is done by sending a parameter block recognised by the driver causing the corresponding device to perform the corresponding operation. All I/O requests are passed to the driver using the standard Input/Output Request Packet, or IRP structures.

  • Data Modes

    FarSync adapters support HDLC-framed, transparent (bitstream) data and asynchronous modes. All the mode can be set on a per port basis.

  • HDLC mode

    HDLC Mode is the normal data mode in which FarSync adapters operate. An HDLC frame uses flags to determine the beginning and end of a frame. These flags provide frame synchronisation. One flag may be used as both an end flag for one frame and the start flag for the next frame. Although FarSync adapters do not transmit such shared flags, they can receive and correctly handle them.

    An HDLC frame typically consists of an opening flag, followed by an address field, a control field, an information field, a cyclic redundancy check (CRC) field, and, finally, a closing flag. As far as the FarSync driver is concerned the address, control and information fields are just data. Frames maintain data transparency by a process called zero-insertion and deletion. When transmitting data, the transmitter inserts a zero after five consecutive ones. When receiving data, between opening and closing flags, the receiver deletes any zero received after five consecutive ones. Zero insertion and deletion is sometimes called bit stuffing and unstuffing and also ZBID.

  • Transparent mode

    The FarSync adapter can also be run in a Transparent Mode, also call bitstream mode. Transparent Mode disables zero insertion and deletion, CRC generation and checking, abort generation, and opening/closing flag generation. Generally for data transmission the application should continuously supply data at a sufficient rate for the line speed so that there are no breaks in transmission. For data reception the application should provide empty buffers at a sufficient rate for the line speed to ensure that no received data is lost.

    The HDLC controller transmits data exactly as it is loaded in the transmit FIFO, when the transmitter has no more data to send it transmits mark idle, no abort sequence is sent. Abort has no meaning in Transparent Mode as all one's is as valid as any other data sequence. Transparent Mode is useful for transmitting and receiving raw data streams such as MPEG video and audio such as T-DMB (Digital Multimedia Broadcasting) and DAB (Digital Audio Broadcasting) ETI (Ensemble Transport Interface - ETSI EN 300 799) and STI (Service Transport Interface - ETSI EN 300 797).

    Transparent mode also disables the receive byte counter; therefore, short frame and long frame errors are not reported.

    Receive data may not be byte aligned, as the receiver knows nothing of the data format or any synchronising sequences. If receive data needs to be byte aligned then this can be achieved in software on the Host PC.

    The FarSync adapters normally send and receive the LSB of a byte first, this is however configurable to MSB if required. When receiving transparent data, no buffer status is transferred to the buffer descriptors by the SmartDMA. The received data is simply a continuous data stream filling buffers, and the SmartDMA controller keeps cycling through buffers without ever storing an EOP. The receiver will begin receiving as soon as the port is started. It will continue receiving as long as there are buffers available in the receive buffer ring. Each receive block is as big as the buffer allocated for it. If the receive data is marking, then the receive buffers just keep being filled with 0xFF's until there are no buffers available or the port is stopped.

SDCI Test Utility

SDCIDemo provided with the FarSync SDK is intended to demonstrate and test the operation of the SDCI interface. Both HDLC frame and Transparent bitstream modes can be tested. Selection and testing of multiple adapters is supported.

SDCIDemo Configuration Screen

SDCIDemo configuration screen

SDCIDemo Screen Shot during Data Transfer

SDCIDemo screen shot showing data transfer on port A of adapter SDCI2. Displayed colours are user configurable.